NVIDIA designed the Vera CPU to address agentic AI workloads where more of the critical execution path runs on the CPU. Agents execute in sandboxes to run code, call tools, retrieve context, interact with databases, and analyze results before returning information to the model. As many such loops run concurrently across an AI factory, CPU characteristics increasingly shape per‑agent responsiveness and overall throughput.
Agentic workloads demand different CPU attributes than traditional cloud server designs: strong single‑thread progress under full socket load, sufficient memory bandwidth per core, predictable latency under concurrency, and efficient handling of irregular control flow, long dependency chains, and pointer‑heavy data structures. The Vera CPU centers this class of workload around the Olympus core.
This article summarizes the Olympus architecture, its multithreading strategy, the coherency fabric, memory subsystem, and secure scale‑up connectivity that together aim to deliver high single‑thread performance at AI‑factory scale. More technical material is available in the NVIDIA Vera CPU white paper.
Olympus: designed for high IPC and sustained per‑thread progress
Olympus was developed through system‑level co‑design across the Vera Rubin platform (CPUs, GPUs, networking, storage, memory systems, and software). The core is targeted at increasing instructions per cycle (IPC) for highly concurrent AI infrastructure workloads, which are often branch‑heavy, have large instruction footprints, and are latency‑sensitive.
Key Olympus blocks:
- Front end: optimized branch prediction, high‑bandwidth instruction fetch, and a 10‑wide decode engine.
- Mid core: critical‑path acceleration, wide rename/allocation, large reorder buffer and physical register file for deeper out‑of‑order execution.
- Execution engine: broad execution resources for integer, vector, floating‑point, cryptographic, load/store work.
- Cache subsystem: latency‑optimized instruction and data paths, multiple prefetch engines, and a graph prefetcher.
Front end
The front end keeps the core fed with useful instructions across large, branch‑rich stacks such as agent runtimes, interpreters, compilers and graph analytics. Olympus includes a neural branch predictor to improve accuracy on statistically biased branch patterns and can support up to two taken branches per cycle, reducing wrong‑path execution and helping sustain control‑flow throughput for irregular software.
Mid core
Agentic workflows frequently form long chains of dependent operations (interpreting code, traversing objects, managing runtime state, processing tool outputs). Olympus exposes hidden parallelism via a wide rename and allocation engine, a large reorder buffer and extensive physical registers. Features such as memory renaming, value prediction and critical‑path acceleration help cut stalls from pointer‑heavy code and serialized memory operations, improving IPC and single‑thread performance on irregular software paths.
Execution engine
A wide front end is complemented by a balanced execution engine that dynamically schedules across many resource types and uses deep out‑of‑order execution. Because agentic workloads are often limited by irregular control flow, long dependency chains and memory latency rather than frequency alone, Olympus emphasizes higher IPC over raw clock speed to improve single‑thread responsiveness.
Cache subsystem
Agent code often touches runtime objects, retrieval indexes, graphs, sparse data and databases that do not match regular streaming access patterns. Olympus’ cache subsystem uses a deep hierarchy, memory disambiguation and multiple hardware prefetchers (including a graph prefetcher) to reduce effective memory latency and increase memory‑level parallelism for graph analytics, data processing and agent workloads.
Multithreading: NVIDIA Spatial Multithreading (SMT)
Multithreading matters for agent workloads because sandboxes are bursty and interleaved with asynchronous I/O, timers, runtime services and tool orchestration. Traditional simultaneous multithreading (SMT) improves utilization but can create contention and noisy‑neighbor effects between threads competing for branch predictors, decode bandwidth, execution and cache resources.
Vera CPU employs NVIDIA Spatial Multithreading to partition resources more effectively between two hardware threads. The wide Olympus core can operate as a high‑throughput single‑threaded core when maximum per‑thread performance is required (with the sibling thread handling management tasks), or as two more isolated execution contexts when higher thread density is needed. Vera CPU contains 88 Olympus cores and 176 SMT threads to support many concurrent agent tasks while reducing thread‑to‑thread interference and improving latency and throughput predictability.
Coherent fabric and high‑bandwidth memory
A high‑IPC core delivers its value only when the rest of the processor can keep it supplied. Agentic AI, RL, graph analytics and data processing often involve large working sets and irregular access patterns, making fabric bandwidth, cache access, memory bandwidth and latency critical.
Vera CPU pairs Olympus with the NVIDIA Scalable Coherency Fabric (SCF) and SOCAMM2 LPDDR5X memory to balance CPU execution at AI‑factory scale.
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NVIDIA Scalable Coherency Fabric: the SCF is the on‑die coherent fabric connecting cores, shared cache, memory controllers, I/O and NVLink‑C2C. It provides up to 3.4 TB/s of fabric bandwidth and integrates a 164 MB unified L3 cache across all cores. By using a monolithic compute die, Vera CPU avoids the die‑hop latency and variability found in chiplet designs.
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SOCAMM2 LPDDR5X memory: the memory subsystem delivers up to 1.2 TB/s aggregate bandwidth (up to 14 GB/s per core), supplying Olympus cores under high concurrency while consuming substantially less memory power than typical DDR5 or MRDIMM server designs. SOCAMM2 modules are field‑replaceable, bringing enterprise serviceability to LPDDR deployments and offering Reliability, Availability and Serviceability (RAS) features needed in data centers.
Moving data at scale, I/O and Confidential Compute
Beyond execution, the CPU must move data securely and efficiently across an AI factory. Vera CPU integrates coherent NVIDIA NVLink‑C2C, dual‑socket scaling, PCIe 6.4, CXL 3.1 and Confidential Computing features into a balanced platform.
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Dual‑socket scaling: second‑generation NVLink‑C2C provides high‑bandwidth socket‑to‑socket connectivity so both CPUs can operate as a unified, coherent system. Because each socket is presented as a single NUMA domain, dual‑socket systems produce a simple two‑NUMA‑node topology that is easier to program and tune.
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I/O: PCIe 6.4 support and up to 176 PCIe lanes in a dual‑socket configuration enable connectivity for next‑generation networking, storage and accelerators. CXL 3.1 enables coherent memory expansion and composable infrastructure.
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Confidential Compute: Vera Rubin NVL72 extends Confidential Computing across scale‑up AI infrastructure, protecting data in use across CPUs, coherent GPUs and interconnects. Built on Arm CCA/RME with per‑VM encryption keys, it supports confidential VM isolation, secure assignment of TDISP‑capable coherent devices and authenticated C2C encryption across coherent links.
Measured and reported performance
A central measure for agentic workloads is single‑thread performance under full socket load, since many sandboxes and tools run concurrently and each agent step needs sustained per‑thread progress. NVIDIA reports that Vera CPU can deliver up to 1.8× higher performance on agentic workloads (per the provided figure). SPEC CPU® 2026 results were measured internally in July 2026; detailed test configurations and measurement methodology are documented in the Vera CPU white paper.
Conclusion
By combining the Olympus core’s high‑IPC design, NVIDIA Spatial Multithreading, a coherent high‑bandwidth fabric (SCF), SOCAMM2 LPDDR5X memory and scale‑up interconnects, NVIDIA positions the Vera CPU as a CPU platform optimized for the sequential, branch‑heavy, latency‑sensitive software paths typical of agentic AI, reinforcement learning, graph analytics and large‑scale data processing. The architecture aims to preserve per‑thread progress and predictable latency as CPUs scale across AI factories. Further implementation and benchmark details are available in the Vera CPU white paper.
