Bill Dally, Nvidia’s chief scientist, leads roughly 300 researchers who are integrating artificial intelligence into the company’s chip-design workflow. Speaking with Google’s Jeff Dean onstage at Nvidia’s GTC conference in mid-March, Dally outlined both the progress made and the remaining challenges toward more automated GPU design.
Where AI is applied
Nvidia deploys AI across five stages of chip design:
- laying out components (layout),
- designing arithmetic circuits (such as adders and counters),
- general engineering assistance (documentation, code generation, Q&A),
- verifying finished designs (verification),
- exploring novel layouts and architectures.
Whenever Nvidia adopts a new semiconductor manufacturing process — typically to shrink component sizes so more circuitry fits per area of silicon — engineers must rework roughly 2,500–3,000 small, reusable layout blocks or cells, such as logic gates and memory latches. An AI system called NVCell handles much of that task.
NVCell combines a genetic algorithm that proposes candidate layouts with a reinforcement-learning agent that incrementally corrects design-rule violations (for example, wires placed too close together). The agent receives a reward each time it clears a violation and a small penalty for each step it takes, encouraging it to find the shortest path to a compliant design. A rule checker flags violations, and the agent learns how to fix them.
Using NVCell, work that previously occupied eight engineers for roughly ten months can now run overnight on a single GPU. The system’s results match or exceed human designs in terms of cell area, power consumption, and signal propagation delay.
Arithmetic units: PrefixRL
Another reinforcement-learning system, PrefixRL, designs the microscopic circuits inside GPU arithmetic units. The agent is rewarded when a circuit meets timing constraints while minimizing chip area and power draw. Dally said the resulting components are unusually configured but perform 20–30 percent better than human designs by their metrics. For example, a 64-bit adder produced by PrefixRL occupies 25 percent less chip area than an equivalent design from industry-standard tools.
Internal LLMs: ChipNeMo and BugNeMo
Nvidia built two internal large language models called ChipNeMo and BugNeMo. The team fine-tuned open‑weights LLaMA 2 base models (7 billion and 13 billion parameters) on Nvidia’s internal documentation, including low-level design code for every GPU the company has produced and the associated hardware specifications. A 2023 paper described three uses for these domain-adapted models:
- answering engineers’ questions about Nvidia hardware,
- generating code snippets in specialized chip-design languages,
- summarizing bug reports.
In that work, the domain-adapted models matched or outperformed a general-purpose base model five times their size on a range of chip-design tasks.
Verification and remaining hurdles
Verification — confirming that a finished design behaves as intended — is the longest stage of the process. Dally’s team is working to compress verification with AI, but he emphasized that designing an entire GPU end-to-end from a prompt remains a distant objective.
Context and related work
- Nvidia first highlighted NVCell in 2021; the PrefixRL adder appeared in 2022; ChipNeMo was mentioned in 2023.
- An April paper from Verkoran, an AI chip-design startup, described an agentic AI system that autonomously designed a 1.48 GHz RISC‑V CPU from a 219-word specification; the design was validated in simulation but not fabricated.
- Last year, researchers at Princeton and the Indian Institute of Technology Madras used deep learning and an evolutionary algorithm to generate wireless communications circuits that challenged conventional design rules.
- In 2023, Google described using reinforcement learning to place components on the surface of its Tensor Processing Units.
Why this matters
Chip-design search spaces are enormous and only sparsely covered by human intuition. Nvidia’s report that reinforcement-learning agents produce unconventional but measurably superior circuits fits a broader pattern in which AI finds solutions human engineers might not consider. Moreover, because Nvidia uses GPUs to train the AI systems that help design its next-generation GPUs, each chip generation can both speed up the design of the next and yield hardware better suited to running the design tools that helped create it.
Dally’s cautious framing — acknowledging significant progress while tempering expectations about full automation — provides a realistic perspective on how far the field has come and how far it still must go.
