OpenAI used its own AI models to assist in the design of its first custom inference chip, Jalapeño, and together with Broadcom completed the tape‑out in nine months, according to the companies' announcement. That timeframe is substantially shorter than the 18–24 months typically seen for advanced ASIC development.
OpenAI and Broadcom described the project as the fastest ASIC cycle to date in advanced semiconductors. The announcement states that Jalapeño is already running the GPT‑5.3‑Codex‑Spark model at the target power and performance levels.
The companies claim the chip achieves roughly 50% lower inference cost per token compared with current Nvidia GPUs. The Jalapeño is presented as an inference‑optimized ASIC designed specifically for running large language models efficiently.
Why this matters
The semiconductor industry has been using AI to support chip design for some time—Google published work on this topic in 2021—but the common expectation across many teams has remained a two‑year development cycle.
OpenAI's nine‑month tape‑out challenges that assumption: if a newcomer can take a custom design through to tape‑out so rapidly, incumbent teams will need to reassess why their schedules remain at 18–24 months and whether AI‑assisted workflows can compress those timelines.
Implications and open questions
- If verified, the claimed 50% reduction in inference cost per token could give OpenAI operational advantages when serving large models.
- AI‑assisted design that meaningfully shortens development cycles would increase pressure across the industry to adopt similar methods and could accelerate the pace of hardware innovation.
- Independent measurements and third‑party analyses will be necessary to validate the performance and cost claims made about Jalapeño.
The collaboration between OpenAI and Broadcom highlights a growing convergence of software and hardware development, where AI not only runs on silicon but is also becoming a tool for creating the silicon itself.
