NVIDIA argues that agentic AI systems — described as “AI factories” — become economically efficient when the entire stack converts compute and capital into completed user tasks effectively. While GPUs run the models, CPUs handle orchestration, tool execution, and sandboxed computation. Production telemetry from 163,594 agentic sessions shows these workloads are highly variable: over 97% of sessions exhibited unique runtime profiles.
Why multiple specialized CPU types aren’t practical
Real agentic runs do not follow stable runtime profiles. Telemetry indicates execution consists of long sequential chains of reasoning punctuated by brief bursts of parallel work. The dominant sequential path is latency‑bound and largely determines end‑to‑end completion time, while transient fan‑outs require available thread concurrency and low per‑thread latency.
Because of this variability, it is impractical to right‑size a fleet by splitting it across multiple specialized CPU design points. The relevant optimization metric for an agentic CPU fleet is the number of completed user sessions, not raw core count. High core‑count systems can appear efficient on paper but often trade away single‑thread performance needed to minimize latency on the agent’s critical path.
The shape of agent trajectories: length and width
The article frames agentic trajectories with two dimensions: length (how many reasoning steps, tool calls, retries and subtasks make up a user turn) and width (how much work fans out concurrently at each stage). Real examples, like a 33‑minute Claude Code session, show that most of the run time is spent advancing a long sequential trajectory, with intermittent parallel sub‑agent activity creating brief bursts of concurrent work. Even during wide fan‑outs the main agent frequently idles until those parallel tasks complete, making per‑thread latency critical.
Turning off cores and stranded memory
NVIDIA notes that CPUs can temporarily “turn off” cores to boost single‑thread performance, but this can leave memory tied to those cores unused. The paper cites roughly 8 GB of unused memory per turned‑off core, which in some configurations can strand up to 1.5 TB of memory capacity — increasing memory TCO and reducing efficiency.
How Vera targets this operating point
The NVIDIA Vera CPU is presented as a design built for this balanced operating point: enough concurrency to absorb fan‑out bursts, and strong per‑thread responsiveness to keep the latency‑sensitive sequential path moving. Vera uses NVIDIA Olympus cores intended to sustain strong single‑thread performance while the full CPU is active. Key microarchitectural features called out include a wide front end, advanced branch prediction, deep out‑of‑order execution, and a high‑bandwidth memory subsystem to maintain forward progress across large code footprints and branch‑heavy, dependency‑laden workloads.
NVIDIA’s internal estimates for SPEC CPU® 2026 claim that Vera delivers up to 1.5× per‑core agentic performance compared with AMD Venice across four representative agentic workloads (compiler, static analysis, Python‑related benchmarks). The SPEC CPU® 2026 measurements for Vera were made internally in July 2026; further measurement and configuration details are referenced in the NVIDIA Vera CPU Whitepaper.
A single CPU design point for agentic fleets
NVIDIA argues a single, balanced CPU design point like Vera reduces resource fragmentation: cores remain productive during both sequential and parallel phases, attached memory is used effectively rather than left idle, and the fleet need not be divided among multiple specialized CPU types to handle unpredictable tool‑calling patterns. The result, according to the company, is a platform that converts compute, memory bandwidth and power into more completed agent turns, improving AI factory output and fleet economics at scale.
Notes on measurements and acknowledgements
The article states Vera’s SPEC CPU® 2026 results were measured internally in July 2026 and that comparisons to AMD Venice used internal estimates and normalized components. It cites Standard Performance Evaluation Corporation trademarks for SPEC® and SPECrate®. The paper acknowledges contributions from Ivan Goldwasser, Diana Aung, Hannah Coutand, Ian Finder, Benjamin Klieger, Arnav Jaiswal, Dylan Mitic and others.
In summary, NVIDIA positions Vera as a monolithic, low‑latency CPU architecture engineered to balance single‑thread speed, concurrency and memory bandwidth for the variable, latency‑sensitive workloads typical of agent‑based AI fleets.
